Loading-Aware Bit-Interleaver Design

The design of bit interleavers for convolutionally encoded orthogonal frequency-division multiplexing transmission using rate and power loading is analyzed. The study is based on an equivalent channel model consisting of several independent parallel binary input channel (aka. bit levels). Using insights on the non-iterative decoding of bit-interleaved coded modulation and some effects of rate and power loading on the characteristics of the bit levels, we propose a novel design guideline for bit interleavers which leads to significantly better bit-error ratios than the commonly employed random bit interleavers. The advantages of the new design are in particular observable for high spectral efficiencies, where conventional bit-interleaver designs cannot benefit from an adapted rate distribution. The proposed approach does not require additional side information beyond the adapted rate distribution.